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DLVSDigital Logic Visualizing System

Logic Lab

Registers

4-bit register, parallel load, shift register and serial transfer between registers.

4-bit register

Parallel inputs
I3
I2
I1
I0
Register
0
Q3
0
Q2
0
Q1
0
Q0
CLK
Q3
Q2
Q1
Q0

Built from flip-flops

D FF Q3D>Q=0D FF Q2D>Q=0D FF Q1D>Q=0D FF Q0D>Q=00CLK1I30I21I11I0

Four D flip-flops on one clock. Every rising edge copies the four inputs into the register, and the value is held until the next edge.