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DLVSDigital Logic Visualizing System

Logic Lab

Canonical Forms

Turn any expression into a truth table, minterms and maxterms, canonical and standard SOP and POS.

Boolean expression analyser, up to 8 variables

Letters A–Z, 0/1, NOT as ! ~ or ′, AND as & * · or by writing terms together, OR as | or +, XOR as ^.

Simplified forms

Minimal SOPC + A′B + AB′
Minimal POS(A + B + C)(A′ + B′ + C)
NAND–NAND form((··C)′ · (A′·B·)′ · (A·B′·)′)′
NOR–NOR form((A + B + C)′ + (A′ + B′ + C)′)′
Canonical SOP (Σm)A′B′C + A′BC′ + A′BC + AB′C′ + AB′C + ABC
Canonical POS (ΠM)(A + B + C)(A′ + B′ + C)

Circuits made from logic gates

Build with
ABC
0A0B0CF=0

AND gates feed one OR gate. A circle on a gate input is an inverter, so there is one gate per term plus the final gate. Flip the inputs to check the answer.

Build with
ABC
0A0B0CF=0

OR gates feed one AND gate. A circle on a gate input is an inverter, so there is one gate per term plus the final gate. Flip the inputs to check the answer.

Properties

TypeContingent
Ones / rows6 / 8
Depends onA B C
SOP cost3 terms · 5 lits
Self-dualno
Monotoneno
Minterms Σm1, 2, 3, 4, 5, 7
Maxterms ΠM0, 6

Try it live

ABCF = 0 (row 0)

Compare with another expression

Truth table

#ABCF
00000
10011
20101
30111
41001
51011
61100
71111

The first variable is the most significant bit. Simplification uses the same Quine–McCluskey engine as the Logic Solver, with an exact minimum cover. NAND–NAND and NOR–NOR show how the minimal forms map onto a single gate type, which is how many real chips are built. Self-dual means F(x) = ¬F(¬x); monotone means turning an input from 0 to 1 never turns F from 1 to 0.