Logic Lab
Flip-flops
S-R latch, clocked S-R, D, J-K, T and master-slave flip-flops with characteristic tables, excitation tables and state diagrams.
D flip-flop
Inputs: D. They only matter at the clock edge.
On each rising edge Q copies D. It remembers one bit. The timing diagram shows the last few steps: watch Q change only at the clock edges, even when the inputs change in between.
Built from logic gates (its own switches)
A clocked S-R latch with R = D′ (the bubble is an inverter), so the forbidden case can never occur. While CLK is 1, Q follows D; when CLK drops, Q keeps the last value. The wires remember their last values, exactly like the real circuit.
State diagram
Each circle is a value of Q and each arrow is one clock edge. The label is the input that causes that move; X means don’t care. This is the excitation table drawn as a diagram.
Characteristic table
| D | Q | Q⁺ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Q⁺ = D
Excitation table
| Q → Q⁺ | Inputs needed |
|---|---|
| 0 → 0 | D=0 |
| 0 → 1 | D=1 |
| 1 → 0 | D=0 |
| 1 → 1 | D=1 |
The characteristic table says what the flip-flop will do. The excitation table runs the other way: given the change you want, which inputs to apply. X means don’t care.