Logic Lab
Counter Design
Design a counter from a state diagram: state table, excitation table, flip-flop input equations and a self-start check, for D, T, J-K or S-R flip-flops.
0 → 1 → 2 → 4 → 6 → 0
1. State diagram
2. State table with flip-flop excitation
| Present | Next | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 100 | 1 | X | X | 1 | 0 | X |
| 100 | 110 | X | 0 | 1 | X | 0 | X |
| 110 | 000 | X | 1 | X | 1 | 0 | X |
For every flip-flop the excitation table gives the inputs that produce its change from the present bit to the next bit: 0→0: J=0 K=X; 0→1: J=1 K=X; 1→0: J=X K=1; 1→1: J=X K=0.
3. Flip-flop input equations (simplified)
J2 = Q1
K2 = Q1
J1 = Q0 + Q2
K1 = 1
J0 = Q2′·Q1′
K0 = 1
Each equation is simplified with the Karnaugh-map (Quine–McCluskey) engine. The states that are not in the cycle, and the X entries, are don’t cares, which is why the equations are short.
4. Unused states
- 011 → 100 back in the cycle after 1 pulse
- 101 → 110 back in the cycle after 1 pulse
- 111 → 000 back in the cycle after 1 pulse
✓ Self-starting: whatever state the power-up leaves it in, the counter reaches the cycle.
5. Input logic from gates
The gates turn the present state (tap a Q box to change it) into the flip-flop inputs. An equation that is only a constant or a plain variable is a wire and is not drawn.
Design procedure: draw the state diagram, write the state table, use the excitation table of the chosen flip-flop to fill in the inputs, simplify with don’t cares for unused states, then draw the circuit. Switch the flip-flop type above to see how the equations change for the same sequence.